Double-precision Floating-point Operations Research Articles

Design of the vector floating-point unit with high area efficiency

With the development of the information age, there is an increasing trend towards mixed precision and vector operations in floating point arithmetic. Traditional floating-point arithmetic is usually implemented using multiple modules to ensure the required speed. Still, this approach significantly increases area and reduces area efficiency, resulting in the wastage of hardware resources. This paper focuses on optimizing speed and area to improve the area’s efficiency. The proposed floating-point unit designed can perform half-precision, single-precision, and double-precision floating-point operations. Under the TSMC 7 nm process, its maximum operating frequency is increased by 5%–37%, the area is reduced by 33%–58%, and area efficiency is increased by 63%–144%.

Design and Implementation of FPU for Optimised Speed

Currently, each CPU has one or additional Floating Point Units (FPUs) integrated inside it. It is usually utilized in math wide-ranging applications, such as digital signal processing. It is found in places be established in engineering, medical and military fields in adding along to in different fields requiring audio, image or video handling. A high-speed and energy-efficient floating point unit is naturally needed in the electronics diligence as an arithmetic unit in microprocessors. The most operations accounting 95% of conformist FPU are multiplication and addition. Many applications need the speedy execution of arithmetic operations. In the existing system, the FPM(Floating Point Multiplication) and FPA(Floating Point Addition) have more delay and fewer speed and fewer throughput. The demand for high speed and throughput intended to design the multiplier and adder blocks within the FPM (Floating point multiplication)and FPA(Floating Point Addition) in a format of single precision floating point and double-precision floating point operation is internally pipelined to achieve high throughput and these are supported by the IEEE 754 standard floating point representations. This is designed with the Verilog code using Xilinx ISE 14.5 software tool is employed to code and verify the ensuing waveforms of the designed code.

A GPU-based coupled SPH-DEM method for particle-fluid flow with free surfaces

Particle-fluid flows with free-surfaces are commonly encountered in many industrial processes, such as wet ball milling, slurry transport and mixing. Accurate prediction of particle behaviors in these systems is critical to establish fundamental understandings of the processes, however the presence of the free-surface makes modelling them a challenge for most traditional, continuum, multi-phase methodologies. Coupling of smoothed particle hydrodynamics and discrete element method (SPH-DEM) has the potential to be an effective numerical method to achieve this goal. However, practical application of this method remains challenging due to high computational demands. In this work, a general purposed SPH-DEM model that runs entirely on a Graphic Processing Unit (GPU) is developed to accelerate the simulation. Fluid-solid coupling is based on local averaging techniques and, to accelerate neighbor searching, a dual-grid searching approach is adapted to a GPU architecture to tackle the size difference in the searching area between SPH and DEM. Simulation results compare well with experimental results on dam-breaking of a free-surface flow and particle-fluid flow both qualitatively and quantitatively, confirming the validity of the developed model. More than 10 million fluid particles can be simulated on a single GPU using double-precision floating point operations. A linear scalability of calculation time with the number of particles is obtained for both single-phase and two-phase flows. Practical application of the developed model is demonstrated by simulations of an agitated tubular reactor and a rotating drum, showing its capability in handling complex engineering problems involving both free-surfaces and particle-fluid interactions.

Long-time simulations with complex code using multiple nodes of Intel Xeon Phi Knights Landing

Abstract Modern partial differential equation (PDE) models across scientific disciplines require sophisticated numerical methods resulting in complex codes as well as large numbers of simulations for analysis like parameter studies and uncertainty quantification. To evaluate the behavior of the model for sufficiently long times, for instance, to compare to laboratory time scales, often requires long-time simulations with small time steps and high mesh resolutions. This motivates the need for very efficient numerical methods and the use of parallel computing on the most recent modern architectures. We use complex code resulting from a PDE model of calcium dynamics in a heart cell to analyze the performance of the recently released Intel Xeon Phi Knights Landing (KNL). The KNL is a second-generation many-integrated-core (MIC) processor released in 2016 with a theoretical peak performance of over 3 TFLOP/s of double-precision floating-point operations for which complex codes can be easily ported because of the x86 compatibility of each KNL core. We demonstrate the benefit of hybrid MPI+OpenMP code when implemented effectively and run efficiently on the KNL including on multiple KNL nodes. For multi-KNL runs for our sample code, it is shown to be optimal to use all cores of each KNL, one MPI process on every other tile, and only two of the maximum of four threads per core.

A GPU based compressible multiphase hydrocode for modelling violent hydrodynamic impact problems

This paper presents a GPU based compressible multiphase hydrocode for modelling violent hydrodynamic impacts under harsh conditions such as slamming and underwater explosion. An effort is made to extend a one-dimensional five-equation reduced model (Kapila et al., 2001) to compute three-dimensional hydrodynamic impact problems on modern graphics hardware. In order to deal with free-surface problems such as water waves, gravitational terms, which are initially absent from the original model, are now considered and included in the governing equations. A third-order finite volume based MUSCL scheme is applied to discretise the integral form of the governing equations. The numerical flux across a mesh cell face is estimated by means of the HLLC approximate Riemann solver. The serial CPU program is firstly parallelised on multi-core CPUs with the OpenMP programming model and then further accelerated on many-core graphics processing units (GPUs) using the CUDA C programming language. To balance memory usage, computing efficiency and accuracy on multi- and many-core processors, a mixture of single and double precision floating-point operations is implemented. The most important data like conservative flow variables are handled with double-precision dynamic arrays, whilst all the other variables/arrays like fluxes, residual and source terms are treated in single precision. Several benchmark test cases including water-air shock tubes, one-dimensional liquid cavitation tube, dam break, 2D cylindrical underwater explosion near a planar rigid wall, 3D spherical explosion in a rigid cylindrical container and water entry of a 3D rigid flat plate have been calculated using the present approach. The obtained results agree well with experiments, exact solutions and other independent numerical computations. This demonstrates the capability of the present approach to deal with not only violent free-surface impact problems but also hull cavitation associated with underwater explosions. Performance analysis reveals that the running time cost of numerical simulations is dramatically reduced by use of GPUs with much less consumption of electrical energy than on the CPU.

Performance improvements of differential operators code for MPS method on GPU

In the present study, performance improvements of the particle search and particle interaction calculation steps constituting the performance bottleneck in the moving particle simulation method are achieved by developing GPU-compatible algorithms for many core processor architectures. In the improvements of particle search, bucket loops of the cell-linked list are changed to a loop structure having fewer local variables and the linked list and the forward star of particle search algorithms within a bucket are compared. In the particle interaction calculation, the problem of the ratio of particles within the interaction domain to the neighboring particle candidates being quite low is improved. By these improvements, a performance efficiency of 24.7 % can be achieved for the first-order polynomial approximation scheme using NVIDIA Tesla K20, CUDA-6.5, and double-precision floating-point operations.

Acceleration of computer-generated hologram by Greatly Reduced Array of Processor Element with Data Reduction

We have implemented a computer-generated hologram (CGH) calculation on Greatly Reduced Array of Processor Element with Data Reduction (GRAPE-DR) processors. The cost of CGH calculation is enormous, but CGH calculation is well suited to parallel computation. The GRAPE-DR is a multicore processor that has 512 processor elements. The GRAPE-DR supports a double-precision floating-point operation and can perform CGH calculation with high accuracy. The calculation speed of the GRAPE-DR system is seven times faster than that of a personal computer with an Intel Core i7-950 processor.

A new CUDA-based GPU implementation of the two-dimensional Athena code

Abstract We present a new version of the Athena code, which solves magnetohydrodynamic equations in two-dimensional space. This new implementation, which we have named Athena-GPU, uses CUDA architecture to allow the code execution on Graphical Processor Unit (GPU). The Athena-GPU code is an unofficial, modified version of the Athena code which was originally designed for Central Processor Unit (CPU) architecture. We perform numerical tests based on the original Athena-CPU code and its GPU counterpart to make a performance analysis, which includes execution time, precision differences and accuracy. We narrowed our tests and analysis only to double precision floating point operations and two-dimensional test cases. Our comparison shows that results are similar for both two versions of the code, which confirms correctness of our CUDA-based implementation. Our tests reveal that the Athena-GPU code can be 2 to 15-times faster than the Athena-CPU code, depending on test cases, the size of a problem and hardware configuration.

Sampling Compton Scattering by Kahn's method on GPU

The Monte Carlo simulation of particle transport does not solve an explicit equation, but rather obtains answers by sampling individual particles and recording some aspects of their average behavior. For the incident energy of particles below 1.5 MeV, the Compton scattering process is sampled exactly by Kahn's method. This paper focuses on accelerating sampling the Compton scattering of Kahn's method on GPU. The sampling procedures are distributed to the massive thread level parallelism of GPU architecture with CUDA programming model. Experimental results show that the speedup of the GPU implementation on one NVIDIA M2050 chip ranges from 3.10 compared with one Intel Xeon X5670 chip to 8.51 compared with one Intel Xeon X5355 chip with full double precision floating point operations.

Parallel, Distributed and Network-based Computing: an Application Perspective

Parallel, distributed and network-based computing is a continuosly evolving field, driven by progress in microprocessor architecture and interconnection technology, as well as by the needs of computing- and data-intensive applications in science and engineering, and, more recently, in business. This field is currently undergoing a significant change, because of the development of multicore and manycore processors, GPUs, and FPGAs, which are the new building blocks of parallel architectures. At the other end of the parallel and distributed computing scenario, computational grids are far from being a mature infrastructure and are evolving toward cloud computing, to get a higher level of virtualization. The availability of programming models, algorithms and software tools capable of harnessing the processing power offered by the new technologies is a key issue to make them usable by application developers. This special issue provides a view of the efforts carried out in this direction. Barlas introduces an optimization approach for reducing data communication and load imbalance in medical image matching on Grids. Binzenhofer et al. present a distributed and scalable algorithm to monitor a p2p network. Cesario and Talia discuss the use of data mining models and services on Grid systems for analysis of large data repositories. Danelutto et al. describe a performance model for component-based applications with stream communication semantics running on Grids. Danese et al. describe a FPGA-based coprocessor to accelerate double precision floating point operations in high-performance applications. Gross and Marquardt introduce a graphical editor providing abstractions from base technology for user-friendly configuration of Ubiquitous Computing environments. The papers collected here are selected extended versions of papers presented at PDP 2007, the Fifteenth Euromicro Conference on Parallel, Distributed and Network-based Processing, held in Naples, Italy, in February 2007. The conference was organized by the Institute for High-Performance Computing and Networking (ICAR) of the Italian National Research Council (CNR) in collaboration with the Second University of Naples, the University of Naples Parthenope and the University of Naples Federico II. We thank the editors of Scalable Computing: Practice and Experience for providing us the opportunity of publishing this issue, the authors for their contributions, and the referees for their precious help in selecting good-quality papers. Pasqua D'Ambra Institute for High-Performance Computing and Networking (ICAR), CNR Naples, Italy pasqua.dambra@cnr.it Daniela di Serafino Department of Mathematics, Second University of Naples Caserta, Italy daniela.diserafino@unina2.it Mario Rosario Guarracino Institute for High-Performance Computing and Networking (ICAR), CNR Naples, Italy mario.guarracino@cnr.it Francesca Perla Department of Statistics and Mathematics for Economic Research, University of Naples Parthenope Naples, Italy francesca.perla@uniparthenope.it

A new error-free floating-point summation algorithm

Summation is a basic operation in scientific computing; furthermore division-free arithmetic computations can be boiled down to summation. We propose a new summation algorithm, which consists of double-precision floating-point operations and outputs the error-free sums. The computational time is proportional to the condition number of the problem, is low according to both our estimates and extensive experiments, and further decreases for producing faithful rounding of the sum, rather than its error-free value.

An Accelerator for Physics Simulations

An accelerator based on field-programmable gate array (FPGA) technology accelerates double-precision floating-point operations present in the energy calculation of Monte Carlo-Metropolis simulations. The accelerator uses COTS components and is scalable in terms of clock frequency, memory capability, and number of computing units. It could also be part of a cluster of accelerated workstations.

MULTIPROCESSOR RUNTIME SUPPORT FOR FINE-GRAINED, IRREGULAR DAGS

We examine multiprocessor runtime support for fine-grained, irregular directed acyclic graphs (DAGs) such as those that arise from sparse-matrix triangular solves. We conduct our experiments on the CM-5, whose lower latencies and active-message support allow us to achieve unprecedented speedups for a general multiprocessor. Where as previous implementations have maximum speedups of less than 4 on even simple banded matrices, we are able to obtain scalable performance on extremely small and irregular problems. On a matrix with only 5300 rows, we are able to achieve scalable performance with a speedup of 34 for 128 processors, resulting in an absolute performance of over 33 million double-precision floating point operations per second. We achieve these speedups with non-matrix-specific methods which are applicable to any DAG. We compare a range of run-time preprocessed and dynamic approaches on matrices from the Harwell-Boeing benchmark set. Although precomputed data distributions and execution schedules produce the best performance, we find that it is challenging to keep their cost low enough to make them worthwhile on small, fine-grained problems. Additionally, we find that a policy of frequent network polling can reduce communication overhead by a factor of three over the standard CM-5 policies. We present a detailed study of runtime overheads and demonstrate that send and receive processor overhead still dominate these applications on the CM-5. We conclude that these applications would highly benefit from architectural support for low-overhead communication.

The TMS390C602A floating-point coprocessor for Sparc systems

A recent Sparc (scalable processor architecture) processor consists of a two-chip configuration, containing the TMS390C601 integer unit (IU) and the TMS390C602A floating-point unit (FPU). The second device, an innovative coprocessor that lets the processor execute single- or double-precision floating-point instructions concurrently with IU operations is described. Dedicated floating-point hardware in the FPU increases the performance of the system. Running at clock periods as small as 20 ns, the chip should deliver 5.5 million double-precision floating-point operations per second under the Linpack benchmark (50-MHz clock rate). The FPU provides single- and double-precision arithmetic functions: addition, subtraction, multiplication, division, square root, compare, and convert. To minimize its math unit's latency, the FPU uses a highly parallel architecture requiring separate math units to optimize additions and multiplications. Traps stop the execution of a program to jump to software routine for handling data-dependent errors or to execute instructions not implemented in the hardware. Benchmark results are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

A 1-million transistor 64-b microprocessor has been fabricated using 0.8- mu m double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit. >